Methods and apparatus for improving the resolution of well logging measurements



July 22, 1969 V N. A.scHus1-ER 3,457,500

METHODS AND APPARATUS FOR IMPROVING THE RESOLUTION OF WELL LOGGING MEASUREMENTS July 22. 1969 N. A. scHus'rc-:R 3,457,500

` METHODS AND APPARATUS FOR IMPROVING THE RESOLUTICN OF WELL LOGGING MEASUREMENTS Filed June 5. 1967 8 Sheets--Sheet 2 INVENTOR ATTORNEY Juy 22, 1969 N. A. scHUsrl-:R 3,457,500

METHODS AND APPARATUS FOR IMPRovING THE RESOLUTION oF WELL LOGGING MEASUREMENTS Filed June 5. 1967 8 Shams-Sheet 5 f/VfGR/l T60 ERROR A 61V/ 700 BYcuM July 22. 1969 N. A. scHusrl-:R ,457,500

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ATTORNE Y July 22, 1969 N. A. scHusTER 3,457,500 METHODS AND APPARATUS FOR IMPROVING THE RESOLUTION` OF WELL LOGGING MEASUREMENTS Filed June 5. 1967 esheetsusneet 5 www# TTORNE Y July 22, 1969 N. A. scHusrER 3,457,500

METHODS AND APPARATUS FOR IMPROVING THE RESOLUTION OF WELL LOGGING MEASUREMENTS ATTORNE Y lJuly 2z, 1969 N. A. SCHUSTER METHODS AND APPARATUS FOR IMPROVING THE RESOLUTION OF WELL LOGGING Filed June 5, 1967 MEASUREMENTS 8 Sheets-Sheet 7 July 22, 1969 N. A. scHusrr-:R

METHfJIbf- ANU APPARATUS FON IMPROVlNG 'IHl". RESUIJU'IION Ol WELL; LOUGLNG MIfJASURIlMEN'lS 8 Sheets-Sheet. i

Filed June 5, 1967 United States Patent O 3,457,500 METHODS AND APPARATUS FOR IMPROV- ING THE RESOLUTION OF WELL LOGGING MEASUREMENTS Nick A. Schuster, Houston, Tex., assignor to Schlumberger Technology Corporation, Houston, Tex., a corporation of Texas Filed June 5, 1967, ser. No. 643,582 Int. Cl. G01v 3/18 U.S. Cl. 324-1 26 Claims ABSTRACT OF THE DISCLOSURE The disclosure of this invention -describes an error correction technique for use with signal processing apparatus of the type wherein a signal derived from well logging appratus for investigating subsurface earth formations is combined with at least one other signal in a desired manner to produce a computed signal. The computed signal, which is an improved indication of the subsurface formations, is stored in memory and subsequently read out for combination with a new derived signal to produce a new computed signal. The error correction technique involves applying various logic schemes to the computed signals, based on certain relationships which describe the propagation of errors from one computed signal to the next. For example, in one case, the error was found to propagate in an oscillatory manner. Apparatus is shown for finding this error, based on this oscillatory propagation, which apparatus subtracts one computed signal from the next and reverses the polarity of the difference signal from time to time. The varying polarity difference signal is then integrated, the integrated value being used to determine the presence of an error in accordance with various logic schemes. To insure that true formation signals are not being confused as errors, a suiliciently long interval of the formations is considered to satisfy the probability that the true earth formation values will not have such an oscillatory nature lover a long interval.

This invention relates to signal processing methods and apparatus for processing well logging measurement signals for providing improved indications of subsurface conditions or characteristics.

In the logging of subsurface earth formations surrounding a borehole drilled into the earth, investigating apparatus is moved through the borehole and investigates the surrounding earth formations to provide an output signal which varies in accordance with variations of the investigated characteristic of the adjoining earth formations. ln electrical logging, for example, the output signal varies in accordance with the electrical resistivity or conductivity of the subsurface earth formations. In any case, it is often desirable that the investigating apparatus respond to only a relatively limited portion of the forma tion material which is adjacent the apparatus at any given instant. For example, it is frequently desired that the vertical resolution of the investigating apparatus be sensitive to only a limited vertical interval of the adjoining earth formations. By so doing, earth formation beds can be more accurately investigated.

When speaking of vertical resolution of an investigating apparatus, the vertical geometrical factor (hereinafter called V.G.F.) is frequently utilized to more accurately describe this vertical resolution. The V.G.F. of an induction logging type investigating apparatus, for example, can be defined as the relative response of the investigating apparatus as a function of relative borehole depth as the investigating apparatus passes from oo to -l-eo through a thin conductive bed extending radially outward from "ice the borehole to infinity and surrounded by beds of zero conductivity. To make it eariser to use, the V.G.F. is usually normalized to one Thus,

+ X da is made equal to one where X is the relative response and dz is a depth increment along the borehole axis. This same procedure can be used to find the V.G.F. if other formation characteristics than conductivity (or its reciprocal, resistivity) are being investigated, i.e. if other than induction logging type investigating apparatus is being utilized.

However, many investigating apparatus respond to a greater vertical region than desired (i.e., they do not have the most desirable V.G.F.). `One technique for correcting this is to provide additional transducer elements in the downhole investigating apparatus to compensate for or to cancel the undesired portion of the response so that the effective vertical resolution of the apparatus is substantially improved. For example, in logging by electromagnetic principles, which is referred to as induction logging, so-called focusing coils are added to the downhole investigating apparatus to cancel to a large extent the response of the apparatus to the so-called shoulder regions lying immediately above and below the desired vertical region of response of the investigating apparatus. However, further problems arise whenever additional transducer elements are added. One such problem is that more apparatus must be placed in the downhole investigating apparatus thus making the downhole investigating apparatus more complex and usually more expensive. Because of harsh downhole environmental conditions, it is desirable to move circuit complexities to the surface of the earth. Other problems concerning the quality of the measurement may also occur. For example, in induction logging, as more coils are added to improve the vertical focusing, the depth of the investigation of the apparatus in a horizontal or radial direction tends to decrease.

Another way of improving the effective vertical resolution of the downhole investigating apparatus is by utilizing the signal processing or computing techniques set forth in U.S. Patent No. 3,166,709 granted to H. G. Doll on Ian. 19, 1965'. This Doll patent teaches the principle of temporarily storing or memorizing well logging signals obtained at various vertically spaced depth levels in the borehole. These stored signals are then combined in an appropriate manner to produce a resultant signal corresponding to the signal that would have been obtained with an investigating apparatus having better vertical resolution. This process is sometimes referred to as computed focusing. The resultant signal is a computed signal and the relative depth levels corresponding to the stored signals which are being combined at any given instant are called computing stations. These computing stations are defined relative to the investigating apparatus, and therefore effectively more through the borehole as the investigating apparatus moves through the borehole. The relative depth level to which the resultant signal is referenced is called the center point or recording point of the investigating system.

3 'l Another way of improving the vertical resolution by signal processing techniques are the techniques shown in copending application Ser. No. 605,424 by Nick A. Schuster, filed on Dec. 28, 1966. Among other things, these techniques enable the use of a much larger effective number of computing stations for a memory system of given capacity. In a more general sense they enable more Sophisticated forms of signal processing to be performed with relatively small memory systems of convenient size for use at the well site. Utilizing the signal processing techniques of the Schuster copending application, any errors introduced into the signal processing system will be automatically and quickly eliminated for investigating apparatus having many types of V.G.F.s

However, some investigating apparatus may have V.G.F.s which do not lend themselves to this automatic cancellation of errors. The present application describes a technique which can be utilized in accordance with the previous Schuster copending application to correct for errors which have crept into the signal processing system.

It is an object of the invention therefore, to provide new and improved methods and apparatus for processing well logging measurement signals wherein more accurate measurements can be obtained. It is another object of the invention to provide new and improved methods and apparatus for processing well logging measurement signals wherein errors induced into the signal processing system can be corrected.

In accordance with one feature of the present invention, apparatus for processing well logging signals comprises means for deriving signals representative of a characteristic of the earth formations surrounding a borehole and combining means for combining selected derived signals with at least one other signal to provide computed signals representative of the formation characteristic at given depth levels correlated with the depth levels of the derived signals. The apparatus further comprises memory means for storing the computed signals, means for reading out the computed signals from the memory means and supplying at least one read-out computed signal to the combining means for combination with the derived signals to cancel out a selected formation response portion of each derived signal, i.e., a selected portion of the derived signal V.G.F. The apparatus further comprises means responsive to the relative amplitude of selected computed signals, at least one of which is a fread-out computed sngal, for detecting the presence of an error in the computed signals and cancelling out the detected error in at least one computed signal.

In accordance with another feature of the present invention, a method of processing well logging signals comprises deriving signals .frepresentative of a characteristic of the earth formations surrounding a borehole and combining selected derived signals with at least one other signal to provide computed signals representative of the formation characteristic at given depth levels correlated with the depth levels of the derived signals. The method further comprises storing the computed signals, reading out the computed signals from the memory means and supplying at least one read-out computed signal to the combining means for combination with each derived signal to cancel out a selected portion of the formation response of each derived signal. The method further comprises detecting the presence of an error in the computed signals in response to selected computed signals, at least one of which is a read-out computed signal, and cancelling out the detected error in at least one computed signal.

For a better understanding of the present invention, together with other and further objects thereof, reference is had to the following description taken in connection -with the accompanying drawings, the scope of the invenwith a schematic representation of one embodiment of electrical circuitry for processing well logging signals derived from a downhole well logging apparatus in accordance with the present invention;

FIGURE 2 shows the V.G.F. of the downhole investigating apparatus of FIGURE 1 at various depth levels in the borehole along with various earth slabs investigated by the downhole investigating apparatus for purposes of explaining the theory ofthe present invention;

FIGURE 3 shows a plot of amplitude versus depth at a selected point in the FIGURE 1 circuit;

FIGURE 4 shows an alternative circuit arrangement that could be substituted for a portion of the FIGURE 1 apparatus;

FIGURE 5 shows a plot of amplitude versus depth at a selected point in the FIGURE 4 circuitry;

FIGURE 6 shows another embodiment of circuitry that could be substituted for a portion of the FIGURE l apparatus;

FIGURE 7 shows a plot of amplitude versus depth a a selected point in the FIGURE 6 circuitry;

FIGURE 8 shows another embodiment of circuitry that could be utilized with the FIGURE 1 apparatus;

FIGURE 9 shows another embodiment of circuitry which could be utilized with the FIGURE 1 apparatus;

FIGURE 10 shows a plot of amplitude versus depth at a selected point in the FIGURE 8 circuitry;

FIGURE 1l shows another embodiment of electrical circuitry that would be utilized with the FIGURE l apparatus;

FIGURE 12 shows another embodiment of apparatus for processing well logging measurements in accordance with the present invention; and

FIGURE 13 shows the V.G.F. of the FIGURE 12 downhole investigating apparatus at several depth levels in the borehole along with the earth slabs corresponding to these V.G.F.s.

Referring now to FIGURE l, there is shown a downhole investigating apparatus 15 supported in A.a borehole 16 on the end of a cable 17 which is raised and lowered into the borehole by suitable means (not shown). The downhole investigating apparatus 15 includes a coil array 18 suitably wound on a central support member (not shown), the coil array including three transmitter coils and three receiver coils. The minus or plus designations on the coils indicate the polarity with which they lare wound. The coil spacings and number of turns can be designed in accordance with standard induction logging coil design procedure, and thus need not be discussed in detail here.

The downhole investigating apparatus 15 also includes a suitable fluid-tight electronic cartridge 19, which includes an oscillator 20 which supplies current to the transmitter coils through a suitable low value resistor 21. The receiver coils are wound in a series relationship and the voltage developed across the receiver coils is supplied to suitable phase-selective circuits 22 which derives its phasereference signals from the resistor 21. It is to be understood that the downhole investigating apparatus 15 could comprise any type of downhole investigating apparatus, such as those well logging devices known as Sonic, Neutron, etc. (In fact, the customary Sonic tool has a V.G.F. very similar to the original apparatus V.G.F. G1 shown in `FIGURE l.)

In operation, the current supplied to the transmitter coils 4set upa secondary current flow in the adjoining earth formations, which secondary current flow induces a voltage in the receiver coils, which induced voltage is proportional to the secondary current flow and thus proportional to the conductivity of the adjoining earth formations. Shown to the right of the coil array 18 is the V.G.F. G1 of this particular coil array 18. The V.G.F. G1 is broken down into two component parts designated'Gcl and Go2. The V.G.F. portion Gc1 is shown as the hatched line portion of V.G.F. G1 of area A and the V.G.F. portion GGZ is shown as the dotted portion of V.G.F. G1 of area B. The areas A and B are equal to the total area of V.G.F. G1 and are `also equal to each other. The arrow designated SL or C1 represents the record-.ing point of the V.G.F.s G1 and G61, the signal designations Sn and Cn representing the signals produced by V.G.F.s G1 and Gc1 respectively. The narrow designated Cn d1 represents the recording point of V.G.F. Gcg, the signal designation Cn d1 representing the signal produced by the component V.G.F. GGZ.

Before proceeding with the description of the remainder of the FIGURE 1 apparatus, it would be helpful to first discuss what a V.G.F. is. As defined earlier, the V.G.F. is the relative response of the downhole investigating tapparatus to a thin conductive bed extending radially to infinity and surrounded by nonconductive beds, as the investigating apparatus passes from -eo to -i-eo across the conductive bed. The resulting curve obtained represents the signal that would be indicated on a meter as the investigating apparatus transgresses the conductive bed. This meter reading plotted versus depth gives the V.G.F. curve. This V.G.F. has a vertical (borehole axis) point which is designated the center or recording point and in this application, the center or recording point for any given V.G.F. will be designated by an arrow with the corresponding signal which that particular V.G.F. produces (eg. Sn, C d1, etc.). The V.G.F. has a fixed depth position relative to the downhole investigating apparatus and thus, in effect, moves through the borehole with the investigating apparatus. For normalization, the area under the V.G.F. curve must be equal to 1 (i.e.

Another point to be noted about V.G.F.s is that if a signal is increased or reduced in magnitude, the V.G.F. which produced that signal is also increased or reduced in magnitude by the same proportion. Also, the subscript n refers to the depth level currently under investigation. (Except that, in the derivations, more than one depth level must be considered, :and thus n-i-d, etc. refer to depth levels presently considered. However, in the description of the apparatus, the subscript n will always refer to the depth level presently under investigation.)

The output signal from phase-selective circuits 22 is a varying D C. signal proportional to the conductivity of the adjoining earth formations :and is supplied via a conductor pair 23, which passes through the armored multiconductor cable 17, to the surface of the earth. At the surface of the earth, the conductor pair 23 is supplied to the input of a differential amplifier 24, which supplies the ground reference potential for the surface signal processing equipment. The output signal from differential amplifier 24, designated Sn, is supplied through a suitable gate circuit 25 to a weighting function circuit 26a having a weight of l/A, of a weighted adding network 26. The output signal Cr1 from weighted adding network 26, taken across a suitable low value resistor 26C is written into a rotating capacitor memory 27 at a write-in contact 27a through a :suitable low output impedance write amplifier 28, and supplied to a suitable recorder 29. The rorating capacitor memory 27 has two capacitors 28a and 28h, one side of which are grounded and the other side r opened circuited until the respective capacitors come in contact with the write-in or read-out contacts. The memory 27 could comprise, in addition to the rotating capacitor memory shown in FIGURE 1 any suitable type of memory such :as for example the stepping switch operated capacitor memory shown in U.S. Patent No. 3,181,117 granted to W. J. Sloughter on Apr. 27, 1965.

The rotating capacitor memory 27 is rotated in accordance with the movement of the downhole investigating apparatus 15 through the borehole. 'I'his movement is detected by a suitable wheel 30 which is disposed relative to the cable 17 so as to rotate with movement thereof. The rotation of the wheel 30 is communicated to a shaft 31 which is supplied through a suitable differential gear 32 to the rotating memory 27. Another shaft 33 which can be rotated by hand is also supplied to the differential gear 32. The shaft 31 is also supplied to the recorder 29 so as to cause the recording medium thereof to move in accordance with depth of the downhole investigating apparatus 15.

Located a clockwise interval d1 from write-in point 27a is a read-out point 27b which supplies the read-out computed signal Cn d1 through a suitable high input impedance read-out amplifier 34 and gate circuit 35 to the negative input of a differential amplifier 36 and the positive input of a differential amplifier 38a. The computed output signal Cn from the weighted adding network 26 is supplied to the positive input of differential amplifier 36. The output signal from differential amplifier 36, which is a difference signal, designated C--C dl is supplied directly to one input of a suitable switching circuit 37 via a switch 57, and through an inverter 38 to another input of switching circuit 37. Switching circuit 37 is shown as a suitable two position stepping switch which steps back and forth between the two input contacts. The ouput signal from switching circuit 37 is in the form of alternating positive and negative indications of the difference signal Cn-n d1 from differential amplifier 36. The output signal from the common switch Contact 37a of switch 37, which signal is a varying polarity difference signal, is supplied through a suitable inhibit gate 39 to the input of an integrator 40, which could comprise, for example, an operational amplifier type integrator. The voltage output from integrator 40 is applied to an absolute value comparator 41 to which also is supplied a reference voltage V. Absolute voltage comparator 41 can comprise any standard type of voltage comparator circuit with a suitable fullwave rectifying circuit on the input thereof. In this manner, either positive or negative voltages from integrator 40 will be applied to the voltage comparator circuit of absolute value comparator 41 as a voltage having the same polarity as the reference voltage V. Upon the output voltage iE from integrator 40 reaching the absolute value of the reference voltage V, absolute value comparator 41 provides an output signal to an AND gate 42.

To provide the timing pulses for the circuitry of FIG- URE l, the rotating wheel 30 is mechanically coupled via a shaft 31 to a suitable depth pulse generating means 43, which could comprise for example, a standard optical slotted drum which generates pulses at depth intervals d1 apart in response to the movement of the cable 17. These pulses are supplied to a one-shot (monostable multivibrator) which converts the pulses from depth pulse generating means to pulses having a fixed time duration. The output pulses from one-shot 44 are supplied to the control terminals of gates 25 and 35, and switching circuit 37 and to AND gate 42. Each pulse from one-shot 44 causes the switch 37a of switching circuit 37 to switch to the other terminal thereof. The output from AND gate 42 is supplied to the control terminals of gates 45 and 46 and through a suitable delay circuit 47 to the reset inputs of integrators 40 and 48. Since the gates in the FIGURE 1 apparatus are controlled from one-shot `44, itis clear that the signals applied to integrator 40 will be pulses of constant time duration whose magnitudes will be proportional to the desired information. Thus, even though integrator 40 integrates with respect to time, one-shot 44 has removed time as a factor. Additionally, while switching circuit 37 has been shown as a stepping switch for simplicity, it should desirably be an electronic switch vso as to not have a mechanical time delay.

The output pulses from one-shot 44 are also supplied to an integrator 48. Since the pulses from one-shot 44 are of fixed time duration and each pulse indicates a depth travel of d1 of the downhole investigating apparatus 15, integrator 48 will develop an analog output voltage proportional to the depth travel of the downhole investigating apparatus 15. This analog output voltage, designated d for depth interval, is supplied through the gate 46, when opened, to a suitable ratio circuit 49 to which also is supplied the output voltage :tE/2 from integrator 40 when gate 45 is open, the 1/2 being supplied by a suitable voltage dividing network 41a.

The output voltage iE/Zd from ratio circuit 49 is supplied directly to one input of a switching circuit `Sti and through an inverter 51 to the other input of switching circuit 50. The switching circuit 50 is identical, in design to the switching circuit 37 and is also energized by the output pulses from one-shot 44. The output signal from switching circuit 50 is supplied to the minus input of differential amplifier 37, whose output is supplied to a weighting function circuit 2611, having a weight -B/A, of weighted adding network 26.

Now concerning the operation of the FIGURE 1 apparatus, the circuitry comprising differential amplifier 24, gate 25, weighted adding network 26, Write amplifier 28, memory 27, read-out amplier 34, and gate 35, is constructed in accordance with the teachings of the abovementioned copending Schuster application Ser. No. 6015,- 424. The purpose of this signal processing apparatus is to process the derived well logging signals Sn in a manner so as to greatly improve the vertical resolution of the well logging system. In V.G.F. terms, the purpose of this circuitry is to convert the original apparatus V.G.F. G1 to the V.G.F. component G61, which as can be seen in FIG- URE l, has vastly improved vertical resolution. To accomplish this, the V.G.F. component G62 is subtracted from the original apparatus V.G.F. G1 to leave the V.G.F. component G61. The V.G.F. component G62, although subtracted from V.G.F. G1, is shown in an upright position in FIGURE l to more clearly show how it subtracts from the V.G.F. G1. The signal Cn corresponding to the computed V.G.F. component `G61 is then stored in memory 27 to be subsequently read out and combined with the signal derived an interval d1 later to perform the same function again. Thus, it can be seen that the V.G.F. component G62 in FIGURE 1 corresponding to the read-out computed signal C d1 was the computed signal stored in memory 27 an interval d1 earlier (downhole).

In the FIGURE 1 apparatus, this operation is accomplished by supplying the derived signal Sn through gate circuit 25 to weighted adding network 26 where it is cornbined with the read-out computed signal Cn d1 from readout contact 27b which is supplied through read-out amplifier 34, gate 35, and differential amplifier 37 to the weighted adding network 26. The resulting computed signal C11 along with being supplied to recorder 29 for recordation as a function of depth, is written into memory 27, from which it is read-out an interval d1 later for combination with the new derived signal.

Looking now at FIGURE 2, there is shown a plurality of earth formation slabs having conductivities an+2,11, 611+@ an, and 01H11, looking from top to bottom. Shown opposite these earth formation slabs is the original apparatus V.G.F. G1 (shown in rectangular form for simplicity) in a plurality of depth positions. The V.G.F.s

,G2, G3, G4 and G5 represent the V.G.F. G1 in the plurality of positions. The V.G.F. G2 corresponding to the derived signal Sl1 is opposite the earth slabs having conductivities an and n dl, the portion of V.G.F. G2 of area A being opposite the earth formation slab having conductivity trn and the V.G.F. portion of area B -being opposite the slab having conductivity 6 61. The relationship for the derived signal Sn of FIGURE 2 can be written as:

Now remembering that the computed output signal from weighted adding network 26 in FIGURE 1 corresponds to the V.G.F. component G61, it can be seen that the computed value Cn can be substituted for the conductivity value an. Likewise, since the read-out computed signal C,1 ,11 corresponds to the V.G.F. component G62, this readout computed signal C 61l can be substituted for the conductivity value 61H11. Thus Equation l takes the form:

Sn=ACn+BCnd1 (2) Now solving Equation 2 for the computed value Cn:

1 B CnhSn-'cn-dl It can be seen that the weights l/A and -B/A in Equation 3 coincidewith the weighting factors of weighting function circuits 26a and 26h in FIGURE 1.

It was shown in the copending Schuster application Ser. No. 605,424 that if an error crept into the signal processing system, it would be eliminated as the investigating apparatus moves away from the depth level at which the error occurred, provided that the V.G.F. area B is different from the V.G.F. area A. However, this automatic error elimination will not occur if the V.G.F. areas A and B are substantially the same. v

Now, if the V.G.F. areas A and B are equal, then A=B=1/2, since A+B must equal l for normalization. Now substituting these values into Equation (3):

(It is to be noted that the V.G.F.s shown in FIGURES 1 and 2 are not shown normalized as far as the computed V.G.F.s are concerned. Thus, assuming that the V.G.F. G2 in FIGURE 2 is shown normalized, i.e. A-t-Bzl, the Weighted adding network 26, in elect, multiplies this V.G.F. G2 by a factor of 2 such that the computed V.G,F. corresponding to the V.G.F. component G61 will be normalized to l and therefore the V.G.F. component G62 corresponding to the read-out computed signal is also normalized to l.)

Now combining Equations l and 4, including the numerical Values for A and B:

However, assume that the read-out computed signal C11 ,11 is not exactly equal to n dl, but instead is equal hole size changes, certain formation boundary or invaded zone conditions, etc.

Now, combining equations 1, 4, and 6:

Cn=2sn`0'n-d1 e="'n"e (7) Now when the investigating apparatus 15 has moved upward an interval d1 to the depth level corresponding to the V.G.F. G2 in FIGURE 2, the relationship for the computed signalC11 1 d1 will be:

Cn+d1=2sn+d1cn=dn+d1+e (8) In like fashion, when the investigating apparatus 15 has moved upward another interval d1 to the depth level corresponding to the V.G.F. G4 in FIGURE 2, the relationship for the computed signal 612,11 will be:

It can be seen that from Equations 6, 7, 8 and 9 for the computed signals Cngdl, Cn, C11+d1, and CM2@ that the error e alternates between positive and negative after each depth interval d1, i.e., -l-e,`-e, +e, 6, etc. This relationship can be utilized to determine the magnitude of the error and correct it. Y

Returning now to FIGURE l, the circuitry within the box 51 comprises means for detecting the error e, computing the magnitude and relative polarity of the error, and generating an error correction signal for correcting the error. The read-out computed signal Cmd1 is subtracted from the new computed signal Cn in differential amplifier 36 and the resulting difference signal C-Cm d1 is reversed in polarity each depth interval of d1 by the switching circuit 37 and inverter 38. The circuitry within the dotted line box 51a includes the logic circuitry for determining if an error is present in the computed signals along with the circuitry for computing the error and generating the necessary error correction signal to the negative input of differential amplifier 38d. This causes the correction of the readout computed signal C 11 and thus stops the propagation of the error e through the computed signals as the downhole investigating apparatus 15 transgresses the adjoining earth formations. The switching circuit 50 insures that the error correction signal is combined with the read-out computed signal CD41 in the proper polarity.

From Equations 6 and 7, the relationship for the output signal from ldifferential amplifier 36 can be written as:

Now considering the computed signals an interval d1 later, combining Equations 7 and 8:

From Equations 10 and 1l it can be seen that if the conductivity values .an and en dl in Equation 10 are the same, then C-C d1 Will be equal to -2e. In like fashion, in Equation 11, if the conductivity values amtdl and a-n are equal, then the output signal from differential amplifier 36, at this point in time, will be equal to +2e'. Now, assuming these conductivity values to be equal, it can be seen that each output signal from switching circuit 37 will have an absolute error magnitude of [2e] and will be of the same polarity. However, this is dependent on the fact that the conductivity values are equal from one earth formation to the next. Obviously, this will seldom be the case. However, if a sufficient interval of the earth formations are considered, then it is clear that there is a strong probability that the conductivity component of the difference signal CTV-Cmd1 from differential amplifier 36 will be substantially zero. Additionally, for any appreciable conductivity components to be supplied to the integratior 40 from switching circuit 37 over a long interval of the earth formations, the conductivity of the adjoining earth formations would have to be of an oscillatory nature since switching circuit 37 is sequentially inverting the polarity of the difference signals Cn-Cn d1. The probability of the earth formation conductivity having an oscillatory nature is substantially small. It is this theory of probability that enables the error correction circuit 51 to accurately determine if there is, in fact, an error propagating through the computed values of conductivity from weighted adding network 26, since after a sufficient depth interval of the formations is considered, there is a strong probability that the conductivity values have cancelled out and only the error component e remains.

The integrator 40 sums up the varying polarity difference signals from switching circuit 37 as a function of depth (not time). The absolute value comparator 41 generates an output signal to AND gate 42 upon the output voltage of integrator 40 attaining the absolute value of the reference voltage V. This reference voltage V is high enough that the theory of probability discussed above is satisfied. To insure that the error correction signal output from error circuit 51 coincides with the read-out computed signal Cn d1 from memory 27 through gate 35, the one-shot 44 which controls gate 35, also controls gates 45 and 46 through AND gate 42. Thus, before an error correction signal can be supplied to differential amplifier 38a, there must be a coincidence of an output signal from absolute value comparator 41 and the pulse from one-shot 44. Since the signal supplied to integrator 40, considering the error component only, is equal to i2e, the voltage on the output of integrator 40 will be proportional to d.2e

where d is the integration interval (i.e., the number of pulses from one-shot 44 times the depth interval d1 between pulses). The voltage dividing network 41a reduces this relationship to ide and the depth signal d from integrator 48 reduces the relationship to ie. After the error cor-rection signal has been generated from error circuit 51, the output signal from AND gate 42, after a suitable delay by delay circuit 47 resets integrators 40 and 48 to begin the operation again. Switching circuit 38 insures that the error correction signal is combined with the read-out computed signal Cn d1 in the proper polarity to cancel out the error e.

Now referring to FIGURE 3, there is shown a plot of the integrated error magnitude, i. e. the output voltage of integrator 40, versus depth. Looking at the solid line plot 52, it can be seen that the integrated error magnitude is increasing in the FIGURE 3 plot as a function of depth. (Note-the plot 52, as well as a remainder of the integrated error magnitude curves are shown as smooth lines for simplicity. In actuality, since the derived signals are being sampled in discrete steps, the integrated error magnitude curves will really take on a stepping or staircase shape.) At the depth measure level m2, the integrated error magnitude reaches the threshold value V of the comparator circuit 41. The depth measure level m1 represents a depth level at which a pulse from one-shot 44 is generated. A depth interval d1 later at depth measure level m3, a pulse from one-shot 44 is generated and at this depth level, an error correction signal is generated from the error circuit 51. The integration depth interval is designated d2 in FIGURE 3. Thus, in the FIGURE 3 case, the error correction signal will be equal to +E/2d2, to correct the error e in the read-out computed signal Cn d1. This insures, then, that the new computed signal Cn will beV accurate (provided no error is present in the new derived signal Sn), and thus the computed signals Cn+d1, CM2@ etc. will be accurate until a new error shows up in the computed signals.

If desired, the differential amplifier 36 could be omitted from the FIGURE 1 apparatus, and only the computed signals Cn supplied to switching circuit 37 and inverter 38. In -this event, the signals supplied to integrator 40 will be reversed in polarity from one earth slab to the next, and the error component will be ie instead of i2e. However, the output voltage from integrator 40 will be fluctuating to a great extent since the conductivity components of each signal applied to integrator 40 will not be substantially cancelled out. Thus, by using the differential amplifier, 36, the conductivity components will be cancelled out for each signal applied to integrator 40 and the error component of each signal will be twice as large, thus providing more desirable results.

It may be desirable to use the signal processing apparatus of FIGURE 1 for investigating earth formations surrounding a borehole wherein there are regions of the adjoining earth formations which have widely varying values of conductivity. It can be seen that when investigating such earth formation regions, the difference signal from differential amplifier 36 may have large voltage components which are representative of only differences in conductivity and not errors. In this event, the voltage output ofintegrator 40 may exceed the threshold voltage V after a relatively short integration interval even though no error is present in the computed signals, i.e., the theory of probability discussed earlier will be diluted.

To take care of this problem, a suitable AC coupled RMS circuit 53 (or differentiator, if desired) is switched to the output of differential amplifier 24 by a suitable singlethrow switch 54 so as to provide an indication of the activity level of the signals derived from the downhole investigating apparatus 15. When the signals derived from the downhole investigating apparatus 15 begin fiuctuating to a great extent, the output voltage from the AC-RMS circuit 53 increases. When this output voltage from circuit 53 increases to a high enough level, a suitable voltage sensitive trigger 55, which could comprise for example, a Schmitt trigger, supplies an output signal to inhibit gate 39 so as to inhibit the signals from switching circuit 37 from being applied to integrator 40. After the investigating apparatus 15 has passed the earth formation zone having such highly fluctuating values of conductivity, the output voltage from circuit 53 drops below the threshold value of trigger 55, thus de-energizing inhibit gate 39 and enabling the output signals from switching circuit 37 t0 again be applied to integrator 40. Although it is not shown, it can be appreciated that it may be desirable to reset the integrators 40 and 48 whenever the highly fluctuating zones are transgressed. To accomplish this, the output from voltage sensitive trigger 55 would be applied to the reset connections of integrators 40 and 48.

Another alternative embodiment for use when the downhole investigating apparatus 15 enters regions of widely fluctuating conductivity, is for the error circuit 51 to give less weight to the difference signals Cn--C d1 from differential amplifier 36 when the downhole investigating apparatus 15 is investigating such regions. In the FIGURE l apparatus, this alternative embodiment is shown by switching the switch 57 to the position to supply the difference signals Cn--C, d1 from differential amplifier 36 through a suitable non-linear circuit, such as the logarithmci function former 56, the output from logarithmic function former 56 being supplied to te switching circuit 37 and inverter 38 through the double-throw switch 57. By so doing, those difference signals from differential amplifier 36 with la-rge magnitudes will be de-emphasized.

It may be desirable, in connection with the FIGURE 1 apparatus, to use other logic for detecting in presence of an error than that shown in FIGURE 1. It may be desirable to correct the read-out computed signal C d1 only after a given depth interval has been considered, provided the output voltage from integrator 40 has attainedthe threshold level V, or it may be desirable to reset integrators 40 and 48 if an error has not been detected after a given interval.

Looking at FIGURE 4, there are shown alternative embodiments of the circuit 51a of FIGURE l for performing these alternative functions. The circuitry of FIGURE 4, shown Within the dotted line box 51a', can be s ubstituted for the circuitry enclosed by the dash line box 51a in FIGURE 1. In the FIGURE 4 circuit, the same circuit elements shown in FIGURE l are also shown in FIGURE 4 with the same numerical designations and thus, need not be discussed further. Likewise, the external connections to the circuit 51a of FIGURE 4 are identical with those in FIGURE 1 and thus, need not be discussed further.

yIn addition to the circuitry of the FIGURE 1 circuit 51a, a suitable counter 60, such as for example, a ring counter, is disposed within the circuit 51a so as to count the pulses from one-shot 44 and after a desired count, supply a pulse to the AND gate 42. Since the output from AND gate 42 initiates the error correction operation, it can be seen that this error correction operation will not take place until the downhole investigating apparatus 15 has transgressed a desired depth interval, and then only if the integrated error magnitude from integrator 40 has reached the threshold value V. This causes the integrator 40 to integrate over a suficient depth interval so as to insure that the theory of probability discussed earlier will be justified. That is, the longer the interval of integration, the better will be the probability that the earth formations do not have oscillating positive 12' through delay circuit 47, along with resetting integrators 40 and 48.

It may also be desirable to reset the integrators if the total integrated value on the output of integrator 40 has not reached a certain specified threshold value within a given depth interval. The reason for using this technique may be that, after a depth interval of sufficient length, if the integrator 40 does not provide a suflicient output voltage, it may be assumed that if there is any voltage on the output of integrator 40 lbelow a certain level, the probability may be greater than this voltage is, in fact, a voltage level which may ordinarily be obtained even if there is no error present in the computed signals. Additionally, it may be assumed that this voltage on the output of integrator 40, if below a specified value, even if it is a genuine error, it is not an error which will have any substantial adverse effects on the computed log recorded by recorder 29 of FIGURE l. The circuitry for accomplishing this latter function is represented in FIGURE 4 by the dotted line 61 connecting the output of counter 60 to the reset inputs of integrators 40 and 48, and counter 60, along with the X-ed out line from ring counter 60 to AND gate 42. Thus in operation, this alternative embodiment in FIGURE 4 will cause the reset of integrators 40 and 48 after a given depth interval if a correction has not been performed by this time. On the other hand, if the output from integrator 40 reaches the threshold value V before this given depth interval, a correction will take place by generating the error correction signal iE/Zd from ratio circuit 49 in the manner discussed in connection with FIGURE l.

It will be obvious to one skilled in the art that various alternatives could be used with the FIGURE 4 circuit. For example, the X-ed out line could be left connected so that the error correction signal would be generated only after the given depth interval, provided the integr-ated value from integrator 40 exceeds the threshold level V, and if not, integrators 40 and 48 and counter 60 would be reset. Additionally, the counter 60, after a given count or interval, could cause the integrators 40 and 48 and counter 60 to be reset if the integrated value of integrator 40 does not exceed a first lower threshold value, and if it is exceeded, to continue counting to a second interval at which time the error correction signal is generated if it excceeds a second higher threshold level.

Referring now to FIGURE 5, there is shown a plot of the integrated error magnitude versus depth for the FIGURE 4 apparatus. In the FIGURE 5 plot, the depth interval d4 is considered to be the depth count of counter 60. First, considering the primary (solid line) embodiment lof FIGURE 4, the plot 62 shows the case Where the integrated error magnitude exceeds the threshold value V before the counter 60 has supplied an output signal to AND gate 42. Thus, the integrated error magnitude continues increasing until counter 60 supplies an output signal after la depth interval d4. Thus, in this case, the output signal from ratio circuit 49 Will be -l-E1/2d4. The plot 63 shows the case where the counter 60 has supplied an output signal to AND gate 42 before the integrated error magnitude has reached the threshold value V. In this case, the error correction output signal from ratio circuit 49 Will be -l-Ez/2d5. Now concerning the lalternative embodiment of the FIGURE 4 apparatus (dotted line in FIG- URE 4), from the dotted line plot 64 in FIGURE 5, it can be seen that the integrated error magnitude has not reached the threshold level V by the depth interval d., corresponding to the count of counter 60, and thus the integrator 40 is reset to zero and the integration process started over again.

Looking now Iat FIGURE 6, there is shown a circuit 51a" that can be utilized in place of the error logic circuit 51a of FIGURE 1. In the FIGURE 6 circuit, the circuit elements having the same designations as certain circuit elements in FIGURE l, and the external connec- 13 tions are the same as in FIGURE 1 and need not be discussed.

Concerning the differences in FIGURE 6, the pulses from one-shot 44 are supplied to the depth integrator 48 through a gate circuit 65. In addition, the integrated value from integrator 40 is supplied to a second absolute value comparator 66 Whose reference voltage is V1. The output from absolute value comparator 66 is supplied to the control terminal of gate 65 and to the reset input of integrator 48 through a suitable diierentiating circuit 67 and a back-biased diode 68.

In operation, the reference value V1 applied to absolute value comparator 66 has a lmagnitude much less than the reference value V lapplied to absolute value comparator 41, thus enabling absolute value comparator 66 to act as an approximate zero crossing detector. When the output of integrator 40 exceeds the reference value'V1, absolute value comparator'66 supplies a positive output voltage of a continuing nature to gate 65 enabling the pulses from one-shot 44 to be counted by integrator 48 to provide a depth function. This insures that integrator 48 Will not begin integrating depth pulses until it is reasonably certain that an error is in fact present in the computed signals Cn. In the event that the integrated value from integrator 40 drops below the reference value V1 before the presence of an error is detected, the voltage output from absolute value comparator 66 Will drop to zero, thus causing a negative going pulse to be applied through diode 68 to the reset input of integrator 48.

Looking now at FIGURE 7, there is shown a plot of the integrated error magnitude Versus depth for the FIG- URE 6 circuitry. Looking at the solid line plot 70 in FIGURE 7, it can be seen that the integrated error magnitude exceeds the threshold level V1 for a short depth interval and then drops below this reference value V1 at measure point m4. Since the integrated error magnitude does not attain the threshold level V of absolute value comparator 41, no error correction operation has taken place yet. Following the plot 70, it can be seen that the integrated error magnitude exceeds the threshold level -V1 for a short interval and eventually cross the threshold level +V1 at depth measure level m5 and increases in magnitude until reaching the threshold level V of comparator 41 at depth measure level m6. Thus, when the next pulse from one-shot 44 is applied to AND gate 42, an error correction signal equal to -i-E/Zd, Where d6 is the depth interval between depth levels m5 and m6, is generated from ratio circuit 49 to correct the read-out computed signal Cnnd1 from memory 27 in FIGURE 1. Thus, it can be seen that with the FIGURE 6 error detection circuit, during depth intervals where no apparent error is detected, the depth integrator 48 will be non-responsive to the depth pulses from one-shot 44. This operation, in eiTect, changes the reference depth level for the depth signal d supplied from integrator 48 of FIGURE 1 so that the depth signal d will have a value to more nearly coincide with the depth interval for which the error was present in the computed signals.

Another alternative arrangement of the FIGURE 6 circuitry is represented by the dotted lines in FIGURE 6. In this alternative arrangement, the output of gate 65 is applied to a counter 7.1, which after reaching a desired count, causes a signal to be applied to AND gate 42, and causes the reset of integrator 40. When integrator 40 is reset, the output of comparator 466 drops to zero, thus causing the reset of integrator 48 and counter 71.

Looking again at FIGURE 7, the dotted line plot` 73 shows the operation of this alternative arrangement of the FIGURE 6 error detection circuit. Assuming that the depth interval which counter 71 counts to, before generating an output pulse is the depth interval d? in FIGURE 7, it can be seen that the integrated error magnitude has not reached the threshold value V after this count dq, and thus the integration operation is reset to begin again. Now following this plot 73, it can be seen that at fthe depth measure level m5, the integrated error magnitude exceeds the threshold level V1 of comparator 66, thus causing integrator 48 to begin integrating the depth pulses from `one-shot 44 and for counter 71 to begin counting for the depth interval d6. However, since the plot 73 reaches the threshold level V of comparator 41 before this count dq, an error correction signal equal to {\E/2d6 is generated from ratio circuit 49 in the same manner as above.

In the preceding embodiments, the error correction operation has only corrected the read-out computed signal (11H11 to inhibit the propagation of the error through the remainder of the computed signals, but has not been concerned with correcting any of the previously computed signals which have already been recorded. However, if the previously computed signals are not to be corrected, then it will more than likely be desirable to set the threshold level of comparator 41 relatively low (or alternatively to set the integration interval relatively low) so that the previously computed signals placed in recorder Z9 will not have reached very large errors. On the other hand, it may be desirable to set the threshold value for the integrated error magnitude (or the integration interval) at a relatively large level so that the theory of probability discussed above, will be justified to a greater extent.

Looking now at FIGURE 8, there is shown apparatus for correcting the previously computed signals before they are applied to the recorder. In FIGURE 8, the circutry of FIGURE l for computing Cn is omitted for brevity, but is considered to be part of the FIGURE 8 apparatus. The error detection and correction circuit 51 is the same as the error circuit 51 of FIGURE 1, but utilizing the FIGURE 6 alternative embodiment (dotted lines of FIGURE 6 are included) as the circuitry within the dotted line box 51a to provide a constant integration interval. The computed signal Cn from weighted adding network 26 and write amplier 28 of FIGURE 1 is written into a suitable rotating capacitor memory 75 at a writeain point 75a. Rotating capacitor memory 75 is essentially the same in construction as rotating capacitor memory 27 of FIGURE l With the exception that rotating capacitor memory 75 has a large number of capacitors (not shown) located at depth intervals d1 apart. Located a depth interval d1 from write-in point 75a is a read-out point 75b which supplies the read-out computed signal `Cn d1 to the read-out amplifier 34 of FIG- URE l. This depth interval d1 in FIGURE 8 is the same as the depth interval d1 shown with memory 27 in FIG- URE l. Thus, memory 75 is substituted for memory 27 in FIGURE 1.

The output signal from gate circuit 35 of FIGURE 1 is supplied to the differential amplifier 36 within error circuit 51 of FIGURE 1. The output from AND gate 42 of the error detection circuit 51 of FIGURE 1, along with being supplied to gates 45, 46 and delay 47 of FIG- URE 6, is supplied to the set input of a flip-Hop 76. The l output from ip-flop 76 is supplied to the control terminals of a pair of gates 77 and 78. The input to gate 78 is supplied from the one-shot 44, the output from gate 78 being supplied to the input of a counter 79, which counts the pulses from one-shot 44 and after a desired count, supplies a pulse to the reset input of Hip-:dop 76. The output from switching circuit 50 of error circuit 51 is supplied to the diierential amplifier 38a of FIGURE 1.

The error correction signal from the Iratio circuit 49 (FIGURE 1) of error circuit 51 is supplied to a suitable memory device 80. The memory device 80 stores the error correction signal iE/Zd from error circuit 51 until a reset pulse is applied from counter 79. The memory y80 could comprise, for example, a shunt capacitor fed from a forward-biased diode, the reset operation of memory 80 taking the form of a switch across the capacitor which causes the capacitor to discharge upon a signal being applied to the reset input of memory 80. The output of memory 80 is applied to a switching circuit 81 like Switching circuit 37 in FIGURE 1 and an inverter 82a, the output from inverter 82a being applied to the other input of switching circuit `81. Switching circuit `81 is driven by one-shot `44. The output from switching circuit 81 is applied through the gate 77 to a differential amplifier 82, the other input to differential amplifier 82 being supplied from a read-out amplifier 483 whose input is connected to a read-out contact 75a of memory 75. The input impedance to differential amplifier 82 must be sufficiently high so as to preserve the charge on the capacitor of memory 80 for multiple read-out.

Concerning the operation of the FIGURE 8 apparatus, upon an error correction signal being generated from ratio circuit vt9 of error circuit 51, this error correction signal iE/Zd is memorized by memory 80. This error correction signal is gated out to differential amplifier 82 by gate 77 at depth intervals of d, apart and in the proper polarity as determined by switching circuit 81. These error correction signals are combined with the signals read out from memory 75 at read-out point 75e in difieren- Itial amplifier 82. The depth interval d8 between read-out points 75b and 75al of memory 75 and is equal to the depth interval count of counter 71 of FIGURE 6. This depth interval d8 is also the depth interval count of counter 79.

When the error correction signal is generated from error circuit 51 and the set input of flip-flop 76 is energized, the computed signal read-out of memory 75 at read-out point 75e, at this time, is the computed signal corresponding to the first depth level at which gate 65 of FIGURE 6 was energized in producing the present error correction signal. Thus, it can be seen that the computed values in memory 75, which were previously computed, are corrected in IFIGURE 8 by supplying the error correction signal stored in memory A80 to differential amplifier 82 each time a pulse is generated from one-shot y44, provided an error has been detected. The read-out computed signal C .d1 from read-out point 7517 of memory 75 is corrected in the same manner as discussed earlier, in the FIGURE 8 apparatus. Thus, after all of the necessary computed signals stored in memory 75 have been corrected, counter 79 generates a pulse to reset memory 80 and flip-flop 76, thus deenergizing gates 77 and 78 and resetting the counter 79 until a new error is detected.

While, in the FIGURE 8 apparatus, the integration interval was fixed by counter 71 of FIGURE 6 so that the interval between read-out points 75b and 75o of FIG- URE 8 could be set at d8, it can be appreciated that apparatus could be constructed to allow the integration interval to vary and still correct the previously computed signals. For example, standard digital techniques could be utilized for this purpose.

It may also be desirable in connection with the present invention to utilize two error circuits in place of one wherein one error circuit is utilized to correct the read-out computed signal Cn d1 which is supplied to weighted adding network 26 of FIGURE l, and the other error circuit is used to correct the computed values stored in the memory 75. In this event, the integration interval (or threshold) of the error circuit which causes the correction of the computed values stored in memory 75 could be set relatively short (or low) so that the length of memory 75 could be relatively small. The integration interval of the error circuit which corrects the read-out computed signal C d1 supplied to weighted adding network 26 of FIGURE 1 could then be set relatively long (either by setting the integration interval itself long or by setting the threshold level V relatively high) so that the theory of probabilities discussed above will more likely be justified. In FIGURE 8, the apparatus for accomplishing this is represented by the dotted line A85 supplying the output signal from gate 35 (FIGURE 1) to a second error detection and correction circuit 51 and a dotted line 85a supplying the pulses from one-shot 44 to this second error detection circuit 51. The error correction signal to ditferential amplifier 38a from error circuit 51 is shown X-ed out for this alternative embodiment while the error correction signal applied to differential amplifier 38a is derived from the second error detection circuit 51.

It is to be understood that there could be many refinements in logic utilized in the present invention to achieve the desired results. For example, circuitry could be utilized for enabling the error circuit to examine a first depth integration interval and determine it error correction is necessary, but not generate Ian error correction signal until the error circuit has had an opportunity to examine a second depth integration interval to determine if the error still exists. If the error exists in these two consecutive depth intervals, the computed signals corresponding to the first depth interval can then be corrected. In this manner, if the downhole investigating apparatus 15 is investigating a zone having violently fluctuating values of conductivity, thus increasing the probability that the error circuit will indicate an error where none exists, the error circuit, by examining a second interval, is not fooled by any erroneous errors indicated during the first interval. Desirably, each interval of integration should be at least as great as the expected depth intervals of such regions of violently fiuctuating conductivities.

Looking now at FIGURE 9, there is shown apparatus for performing the above operation that can be utilized in connection with a portion of the FIGURE l apparatus. Again, in FIGURE 9, that portion of the FIGURE 1 apparatus which performs the same function has been omitted. More specifically, the circuit 51b of FIGURE 9 can be substituted for the error logic circuit 51a of FIG- URE 1 and memory 75 is substituted for memory 27 of FIGURE l. Read-out amplifier 83, inverter 101, switching circuit 102, and differential amplifier 82 of FIGURE 9 comprise circuitry added to FIGURE 9 for correcting the previously computed signals stored in memory 75.

In the FIGURE 9 apparatus, the integrator 40 provides the integrated error magnitude iE, and after a given count by counter 87, supplies this integrated error magnitude :LE through the ygate circuit 88, which is energized by counter 87, to a ratio circuit 89. The depth function d/2 is also supplied to ratio circuit 89, where d is the depth interval corresponding to the count of counter 87. The output signal iE/Zd from ratio circuit 89 is cornpared with a reference value V in an absolute value comparator 90 and if iE/Zd is greater than V, the error correction signal iE/Zd is supplied to one of the memories 91 or 92, as determined by switching circuit 93. The purpose of flip-Hop 94, trigger flip-flop 95, AND gates 96 and 97, diferentiator 103, and gates 98 and 99 is to supply the proper error correction signal from one of memories 91 or 92 through the OR gate 100, switching circuit 102, and inverter 101 to the differential amplifier 82 upon an error being detected in two successive integration intervals. That is, the logic circuitry comprising difterentiator 103, flip-flop 94, trigger flip-flop 95 and AND gates 96 and 97 determines if the presently investigated interval (the interval as determined by counter 87) and the preceding investigated interval have produced error correction signals which exceed the threshold level V, and if so, to correct the computed signals read out of memory 75 from readout contact 75C. Trigger lflip-flop 95 keeps track of which integration interval is the one being presently investigated and which one was previously considered, i.e., which memory, 91 or 92, contains the error correction signal from the preceding integration interval. Flip-flop 94 supplies a signal to AND gates 96 and 97 if an error has been detected by comparator 90, in which case, one of the gates 98 or 99 is opened to allow the error correction signal stored in either memory 91 or 92 (whichever one represents the last preceding integration interval, not the 17 one just considered) to be utilized to correct the computed signals from memory 75 in differential amplifier 82. The nip-flop 94 is reset by the outputpulse from counter 87 only if an error is not detected (Note: the output signal from comparator 90 is of longer duration than the reset pulse from differentiator 103).

Taking an exampleof this, assume an error correction signal is stored in memory 91 for the first integration interval. If an error is detected in the second integration interval, AND gate 96 will become energized from the output of trigger ip-ilop 95, the "1 output of flipop 94, and one-shot 44. Thus, during the third integration interval, memory 91 will produce error correction signals to correct the computed signals read out from memory 75 each time one-shot 44 generates a pulse. The error correction signal for the second integration interval will 'be stored in memory 92. Now, if at the end of the third integration interval, no error is detected, the signal from counter 87 will reset ip-op 94 through differentiator 103 and diode 103a since no signal is generated from comparator 90. Thus, gate 99 -will not be opened to allow correction of the computed signals read out from memory 75 corresponding to the second integration interval during the fourth integration interval.

The read-out computed signal C 1 is corrected by the apparatus comprising OR gate 104, differentiator 105, diode 105e and gate 106. That is, if the logic circuitry has determined that there is a correction to be made, gate 106 is opened by the positive going pulse from diode 105a for a short interval to allow this correction to be made one time only in differential amplifier 38a (FIGURE 1).

Looking at FIGURE 10, there is shown a plot of the error correction signal iE/Zd over the three exampled integration intervals discussed above, as represented by the depth intervals dg, dg' and dg". Assuming that the error correction signal E/ 2d for the integration interval preceding the integration interval dg was less than the reference value V, there will be no error correction operai tion at the end of this first integration interval dg. However, since the error correction signal for thesecond integration interval dg has exceeded the reference value V, the read-out computed signal from memory 75 will be corrected at the end of this second integration interval via gate circuit 106 and` the computed. values stored in memory corresponding to the first integration interval dg will be corrected via OR gate 100. Now, on the third integration interval dg, since the error correction signal magnitude is less than the reference value V, no correction will take place of either the computed signal C1141 read out from memory 75 at read-out point 75bA or the computed signals corresponding to the second integration interval dg. s

If desired, suitable logic circuitry could be implemented for the error correction process to take place only if the error correction signal of the presently investigated in terval is equal to at least the error correction signal of the last preceding integration interval. This is represented in FIGURE 9 by the dotted line circuitry and conductors,

with the Xs indicating those conductors which are notl of memories 91 and 92. In this alternative arrangement of FIGURE 9, the output signal from comparator 107 is supplied to the set input of flip-flop 94'to initiate the error correction operation, in place` of the output Vfrom comparator 90. 'Ille output from comparator 90 is still',

applied to the gate circuit 98 to insure that the error signal has a magnitude at least as great as the reference level V. l

In the preceding embodiments, the interval between capacitors hereinafter called memory. stations, has `been equalv to the interval d1 between the computing stations represented by the arrows Sn and C d1. The interval between depth levels at which the derived Well logging signals Sn from the downhole investigating apparatus 15 were sampled, as determined by one-shot 44 energizing gate 25, is the same depth interval d1 since the sampled well logging signals should be supplied to weighted adding network 26 with each read-out computed signal C d1 from memory 27 or 75. It may be desirable to sample the derived well logging signals at closer intervals than this interval d1 between computing stations. However, when the derived well logging signals are sampled at such close intervals, only one error detection circuit, as shown in the above embodiments, may not suffice. The reason for this is that any error showing up in a computed signal which is written into memory 27 or 75 will not show up again for an interval d1 later, since the computed signal having the error is not read out of memory until an interval d1 later. Thus, this error will not show up in those computed signals corresponding to the depth levels which are other than intervals ndl apart, where n in a positive integer.

Turning now to FIGURE 11, there is shown circuitry for sampling the derived well logging signals at depth Y intervals of less than the distance between computing stations d1. The circuit elements in FIGURE 11 which have the same function as circuit elements in FIGURE 1 have the same numerical designations thereof. The derived signal Sn from differential ampliiier 24 (FIGURE l) is supplied through the gate 25 to weighted adding network 2.6 and write amplifier 28 to a write-in contact 110@ of a rotating capacitor memory which is rotated in a clockwise direction by the shaft from differential gear 32 (FIGURE 1). Memory 110 has memory stations at intervals of i1/3 apart. Located a clockwise interval d1 from write-in contact 110a is a read-out contact 110b which reads out the computed signal Cn d1. This read-out computed signal Cn d, is supplied through the gate 35 and differential amplifier 37a to weighted addingnetwork 26 to be combined with the derived signal Sn in the same manner as in the FIGURE 1 apparatus. The readout computed signal C d1 is subtracted from the computed signal Cu in differential amplifier 36 and the output supplied to inverter 38 and switching circuit 37 in the same manner as in FIGURE'l. In addition to the FIGURE 1 apparatus, there is shown in FIGURE 1l, a three position switching circuit 111 whose three outputs are supplied to separate parallel error logic circuits 112, 113, and 114 which comprises the error circuitry 51a of FIGURE 1 (or one of the other circuit 51a', 51a"). The

timing signals for these three error detection circuits are' supplied from a suitable switching circuit 115, like switching circuit 111, which supplies the pulses from a depth pulse generating means 116y (via one-shot 44) which is similar to depth pulse generating means `43 of FIGURE 1, except that pulse means 116 generates pulses at'depth intervals of f1/3 (i.e., thesignals from switching circuit to error logic circuits 112, 113 and 114 take' the place of the signals from one-shot 44 to circuit 51a of FIGURE 1). The three error correction signal outputs from the error detection circuits 112, 113, and 114 are supplied to an OR gate 117, whose output is supplied to the differential amplifier 37a through the switching circuit 50 and inverter 51. To control switching circuits 37 and 50, the pulses from one-shot 44 are scaled-down by aY factor of three by a suitable scaling device'118, which` then, that the proper error correction signal is combinedin diterential amplifier 37a with the proper read-out computed signal. That is to say, taking an example, integrator 40 of error detection circuit 112 will be responsive to only those computed signals Cn, Cn d1, Cn 2d1, etc., integrator 40 of circuit 113 will be responsive to only the computed signals Cmd1 ,3, Cn 2/3d1, Cn 5/3d1, etc., and integrator 40 of circuit 114 will only be responsive to the computed signals CM2/3,11, CD4/3,11, CD4/3,11, etc.

It is to be understood that any of the above embodiments could be incorporated into the FIGURE 11 embodiment. For example, the FIGURE 11 apparatus could be converted to correct the computed values stored in memory .as in the FIGURE 8 apparatus, etc. 'f Looking now at FIGURE 12, there is shown apparatus for performing the error detection and correction operation of the present invention in combination with a three station computer constructed in accordance with the teachings of the above-mentioned Schuster copending application Ser. No. 605,424. In FIGURE 12, there is shown a downhole investigating apparatus 120 having a measure or recording point and supported in the borehole by the cable 17. Shown to the right of the downhole investigating apparatus 120 is the V.G.F. G6 of this downhole investigating apparatus 120 when it is `at the depth level shown in FIGURE 12. The arrow designated Sn represents the recording point of the V.G.F. G6, Sn being the signal designation for the derived signal produced by the V.G.F. G6. The original apparatus V.G.F. G6 is broken down into three component parts designated G03, G64 and G65 having the signal designations Cn, Cn d1, and C 2d1 and areas A, B, and D respectively. In accordance with the previously mentioned copending Schuster application Ser. No. 605,424, the computed signals Cn d1 and Cn 2d1 are subtracted in the proper weights from the derived signal Sn to produce the computed signal Cn. In V.G.F. terms, the component V.G.F.s G64 and Gc5 are subtracted from the original apparatus V.G.F. G6 to leave the component V.G.F. Gea, but are again shown in an upright position to more clearly show how they subtract from G6.

Looking now at FIGURE 13, there is shown the V.G.F. G6 (shown in rectangular form for simplicity) at a plurality of depth positions opposite a plurality of earth formation slabs designated an+3d1 through en gdl. The

earth formation slabs are of thickness d1 to correspond with the vertical extent of the V.G.F. components G63, Gc., and Gc5. The original apparatus V.G.F.s shown in FIGURE 13 correspond to the downhole investigating apparatus 120 of FIGURE 12 being at intervals d1 apart.

The equation for the derived signal Sn can be writ- Now, substituting the computed signal designation Cn, C d1, and Cn 2d1 for the corresponding conductivity values:

Since the areas A, B and D are equal to one another, it is clear that A=B=D=1/3 since A+B-PD must equal 1 for normalization.

Now rewriting Equation 14 in terms of these numerical values for A, B, and D:

Cn=3Sn Cn-d1"Cn-2d1 Now combining Equations 12, 13 and 15:

This procedure could be followed to solve for the other computed signals Cn d1, Cnndz, etc., in the same manner.

Now assume that the computed values C d1 and C 2d are not equal to the conductivity rvalues n dl and en gdl, but instead are equal to:

where e1' and e2 are error components. Now substituting Equations 17 and 18 into Equation l5:

formation conductivity values, the following expression can be utilized: t

It can be seen that, if no error components `are present, Equation 23 will produce zero integrated Voltage is considered over a sufliciently long depth interval. Now, com- In like fashion, when Expression 23 is applied to the computed values corresponding to other depth levels, the following equations can be written:

Now, if the earth formations are investigated over a suiciently long depth interval, it is seen that the conductivity portions of Equations 24, 25, 26 and 27 will be substantially equal to 0, This is based on the theory of probability again, as before. Looking at just the error components in Equations 24, 25, 26, 27, it can be seen that the errors e1 and e2 will propagatein the following sequence in Equations 24 through 27: 1.5e1-1.5e2, -l-1.5e2, +1.5e1, 1.5e1-1.5e2, etc. This known propagation of the errors in Equations 24-27 provides the basis for detecting and correcting the errors in the computed values. Comparing Equations 24 through 27 with Equations 19 through 22, it can be seen that the error components in both sets of equations are proportional to each other by a factor of 1.5, using the full computed signal value as the recording point or depth level for Equations 24 through 27, i.e., n is the recording level for Equation 24, Cn d1 for Equation 25, etc.

Referring again to FIGURE 12, the signals derived from the downhole investigating apparatus are supplied through the cable 17 to the differential amplifier 24 at the surface ofthe earth in the same manner as in FIG- URE 1. The derived signal Sn from diiferential amplifier 24 is supplied to a weighted adding network 123, whose computed output signal Cn, along with being supplied to a suitable recorder, is written into a suitable rotating memory `124'throngh the write amplifier 28 at write-in contact 12401. Rotating memory 124 is driven in a clockwise direction. The computed signals Cn d1 and Cn 2d, are read-out of'rotating memory 124'at read-out points 124b and 124C through read-out ampliers 125 and 126 respectively and applied through gates 121 and 122 and differential ampliers 134 and 130 to the weighted adding network 123. Gates 25, 121 and 122 are energized from the one-shot 44, as in FIGURE 1. The circuitry just described represents the three station computing process disclosed in the previously mentioned copending Schuster application Ser. No. 605,424. The weighting functions (not shown) of weighted adding network 123 to which the signals Sn, C ,11 and Cum, are applied are l/A,-B/A, and D/A respectively, from Equation 14.

Now concerning the error detection and correction portion of FIGURE l2, the computed signals Cn, C,1 d1, and C, 2,11 are supplied to a weighting network 127 which applies the l, -1/2, and -1/2 to weighting functions to these three computed signals in accordance with Equation 23. The output of weighting circuit 127 is supplied to the Wiper arm of a three position stepping switch 128 having switch positions S1, S2 and S3. The switch positions S1, S2 and S3 are supplied to error detection circuits 129, 129a and 129b respectively. These three error detection logic circuits 129, 129a and 129b are identically constructed, only the error detecting logic circuit 129 being shown in detail. The circuitry for the error detecting logic circuit 129 is the same as error detecting logic-circuit 51a of FIGURE l, with the exception that the scaling circuit 41a of FIGURE l, which has a weight of 1/2 in FIGURE 1, has a weight of in FIGURE 12 and is designated 130.

In FIGURE 12, the AND gate 42 in each of the error detecting logic circuits 129, 129:1 and 129b are tied together so that an error detected in one circuit will produce error correction signals in all three circuits. The outputs from circuits 129, 129m and 129b, taken from the ratio circuit 49 `'of each of these circuits, are supplied in a desired manner to three position stepping switches 128a and 128b. The signals from the wiper arms of stepping switches 128a and 128b are supplied to the negative inputs of differential amplifiers 134 and 130 respectively. The wiper arms of switches 128 and 128a and 128b are stepped in a ganged fashion Whenever a pulse is received by the solenoid 128C from one-shot 44, Thus, the switches are stepped at depth intervals of d1. (Again, switches 128, 12811 and 128b are shown as stepping switches for clarity, but should be fast switching electronic switches.)

In operation, the stepping switch 128 causes the output signal from weighting circuit 127, which should be equal to over a sufficiently long interval if no error is present, to be applied to each of the circuits 129, 129:1 and 12912, thus causing the integrators 40 of each of these circuits to build up an output voltage proportional to any error in the computed signals. If an error is `detected by one of the error detection logic circuits, error correction signals are supplied to diierential amplifiers 134 and 130 from one of the error detection logic circuits via switches 128a and 12811 to correct any error which may exist in the readout computed signals Cn d1 and 11-23? This then insures that the new computed signal Cn Written in to memory 124 is accurate. However, the computed signal 01H11 stored in memory 124 may have an error which was not corrected, and which error will show up again when this computed signal is at read-out point 124C (computed signal C1, 11 now being designated Cn 2d1). Thus, the error correction signal for the read-out computed signal C1141 is stored in a suitable memory 131 after a delay by delay circuit 132. Thisdelay prevents the error correction signal being applied to diiferential amplifier 134 from feeding into differential amplifier 130. Now, when the computed signal C 2,1l is read out of memory 124 to be applied to the weighted adding network 123, the error correction signal stored in memory 131 is applied to diierential ampliiier. 130 through a suitable gate 133 energized by oneshot 44 to provide the necessary correction. Now, all of the computed signals stored in memory 124 are accurate.

Taking an example of this operation, assume that when the switch 128 is in the S1 position, the error component from weighing circuit 127 is -l.5e1-l.5e2; when in the S2 position, it is 1.5e2; and when in the S3 position, it is 1.5e1; and back in the S1 position it is again.-1.5e1-l.5e2, etc. in accordance with Equations 24, 25, 26. In this eX- ample, it is clear that the integrator 40 of error detection circuit 129 will build up a negative voltage at a greater rate than the integrators 40 of error detecting circuits 129a and 129b. Thus, after a given depth interval, AND gate 42 of error detection circuit 129 will produce an output signal, thus indicating an error, when the switch iS in the S1 position. When the switch is in the S1 position, it is clear that the error detection logic circuit 129th connected to the S3 position corresponds to the computed signal an interval d1 earlier and thus the error correction signal from the circuit 129b will pass through the S1' switch position of switch 128a to differential amplifier 134 to correct the computed signal C d1 read out from memory 124. Since the switch position S3 has been supplying an error signal 1.5e1 to error detection logic circuit 129b, the error correction signal generated from circuit 129b will be -|-e1 (the weighting circuit 130 taking out the 1.5). The differential amplifier 134 will invert the polarity of e1 to e1 so as to cancel out this error -i-el.

In like fashion, when the switch 128 is at switch position S1, the switch position S2 corresponds to the computed signal an interval 2d1 earlier, and thus error detection logic circuit 129a generates an error correction signal +e2 through the switch position S1" of switch 128!) to differential amplifier 130 to correct the error in the computed signal C 2d2 read out from memory 124. Now, at an interval d1 after this error correction operation, the signal e1 from circuit 12911, which has been stored in memory 131, is gated out of memory 131 by gate 133 t0 be combined with the read `out computed signal C 2d1l in differential amplifier 130. In like fashion, if one of the other error detection circuits indicates an error first, the switch being in position S2 or S3, one, with a little thought, can follow the conductors through switches 12811 and 128b to see how the errors are corrected. Obviously, either e1 or e2 may be absent in any given situation,

If desired, the error correction signals generated from error circuits 129, 129a and 129b could be utilized to correct all of the computed singals stored in memory which have an error component. Shown to the right of V.G.F. G6 in FIGURE 12 are a plurality of depth levels designated from the bottom up S1, S2, S3, S1, etc. These depth levels are intervals d1 apart and correspond to the similarly designated switch positions of switch 128. Thus, it can be seen that, to reset the computed signals stored in memory, it is merely necessary to take the error correction signal from circuit 129 and reset the computed signal stored in memory corresponding to every depth position S1; the error correction signal from circuit 129a to correct the computed signal stored in memory corresponding to every depth level designated S2; and the error correction signal from circuit 129b to correct the cornputed signals corresponding to the computed signals corresponding to the depth levels designated S3. The circuitry for correcting the computed signals stored in memory has not been shown in FIGURE 12 but should be obvious in construction when considering FIGURES 8 and l2 in conjunction. Additionally, the multiple sampling feature shown in FIGURE ll could be utilized in connection with FIGURE l2, as could anyV of the other embodiments disclosed above.

One skilled in the art, once armed with the teachings of the present invention, could readily apply these teachings to derive the necessary equations and construct the necessary apparatus to provide error correction circuitry in connection with four station computing techniques, iive station, etc. shown in the copending Schuster application. Likewise, other logic techniques to discover the error could be utilized thanthe ones specifically disclosed.

While there have 4been described what are at present considered to be preferred embodiments of this inven- 23 tion, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is, therefore, intended to cover all such changes and modiiications as fall within the true spirit and scope of the invention.

What is claimed is:

1. Apparatus for processing well logging signals, comprising:

(a) means for deriving signals representative of a characteristic of the earth formations surrounding a bore hole, each of the derived signals being representative of the characteristic in a given portion of a formation;

(b) combining means for combining selected derived signals with at least one other signal to provide computed signals representative of the formation characteristic at depth levels correlated with the depth levels of the derived signals, and wherein said computed signals may include an error component;

(c) memory means for storing the computed signals;

(d) means for reading out the computed signals from the memory means and supplying at least one readout computed signal to the combining means as said at least one other signal for combination with the derived signals to cancel out a selected portion of the formation response characteristic of each derived signal; and

(e) error suppression means responsive to the relative amplitudes of selected computed signals, at least one of which is a read-out computed signal, for detecting the presence of an error in the computed signals and cancelling out the detected error in at least one computed signal.

2. The apparatus of claim 1 wherein the error suppression means includes:

(1) detecting means responsive to the computed signals for detecting the presence of an error in the computed signals;

(2) means for computing the magnitude and relative polarity of the error upon the presence of an error being detected by the detecting means;

(3) means for generating an error correction signal of substantially the same magnitude as the computed error and of a polarity to substantially cancel out the detected error in the computed signals; and

(4) means responsive to the generated error correction signal for cancelling out the detected error in at least one computed signal.

3. The apparatus of claim 2 wherein the detecting means includes:

(1) means responsive to the computed signals for providing an integrated function of the computed signals; and

(2) means responsive to the integrated function of the computed signals for determining the presence of an error in the computed signals and enabling the error to be computed and the error correction signal generated.

4. The apparatus of claim 2 wherein the detecting means includes:

(l) means for subtracting each computed signal from the combining means from at least one read-out computed signal read out `from the memory means to provide difference signals;

(2) means for sequentially varying the polarity of the difference signals;

(3) means for integrating the varying polarity difference signals; and

(4) means responsive to the integrated varying polarity difference signals for determining the presence of an error in the computed signals and enabling the error to be computed and the error correction signal supplied to the combining means to cancel out the error.

5. The apparatus of claim 3 wherein the error suppression means further includes:

(1) means responsive to the integrated -function for computing the magnitude and relative polarity of the error upon the presence of an error being indicated by the detecting means; and

(2) means for supplying to the combining means an error correction signal of substantially the same magnitude as the detected error and of the proper polarity so as to substantially cancel out the error in the computed signals.

6. The apparatus of claim 3 wherein the means responsive to the integrated function for determining the presence of an error in the computed signals includes:

(l) comparator means for generating an output signal upon the integrated function exceeding a predete-rmined threshold level; and

( 2) means responsive to the output signal for enabling the error to be computed and the error correction signal generated.

7. The apparatus of claim 3 wherein the detecting means further includes means responsive to the derived well logging signals for inhibiting the computed signals from being integrated when the derived signals are widely iiuctuating as a function of depth.

8. The apparatus of claim 2 wherein the detecting means is responsive to a nonlinear function of the computed signals, the nonlinear function being of the type which minimizes high level signals.

9. The apparatus of claim 3 wherein the means responsive to the integrated function for determining the presence of an error in the computed signals includes:

(1) comparator means for generating a rst output signal upon the integrated function exceeding a predetermined threshold level;

(2) means for generating a second output signal after signals have been derived over a given depth interval of the borehole; and

(3) means for enabling the error to Ibe computed and the error correction signal generated in response to both the iirst and second output signals.

10. The apparatus of claim 9 wherein the second output signal resets the integrator means so that the integration of the Icomputed signals is started over again if the presence of an error has not been detected within said given depth interval of the borehole.

11. The apparatus of claim 3 wherein the means for computing the magnitude and relative polarity of the error includes:

(1) means for providing a depth signal representative of the elapsed depth interval from a selected reference depth level; and

(2) means responsive to the depth signal and the integrated function for computing the error in the computed signals.

12. The apparatus of claim 11 wherein the means for computing the magnitude and relative polarity of the error further includes means responsive to the integrated function for controlling the selected reference depth level of the means for providing a depth signal so that the depth signal supplied to the means for computing the enror will be approximately proportional to the elapsed depth interval for which the error was present in the computed signals.

13. The apparatus of claim 12 wherein the means for controlling the selected reference depth level includes:

(1) means for generating an output control signal upon the absolute value of the integrated function exceeding a given reference level; and

(2) means responsive to the output control signal for changing the selected reference depth level so that the selected reference depth level will more nearly coincide with the depth level at which the error began.

14. The apparatus of claim 2 wherein the means for cancelling the detected error further includes means re- 

